1. Technical Field
The present invention relates generally to an improved data processing system. More particularly, the present invention relates to a method and apparatus for processing control of on-chip data transfers.
2. Description of Related Art
As fabrication techniques for digital logic circuitry continue to improve, chip designers increasingly place more data processing components and logical functions on-chip. As more functionality is placed on-chip, the need for configuring modes of operation for the chip and for checking the status of the chip for the new functionality also increases. Hence, chip designers also desire increasing amounts of mode configuration and status monitoring functionality on the chip.
The placement of all of this functionality on the chip leads to contention for physical resources, which is a major concern while designing chips. Each component requires a certain amount of power that results in heat that must be dissipated. In addition, each component requires a certain amount of physical space. As the ability to shrink circuitry increases, thereby creating more physical space for more components on-chip, the number of components that a designer desires to place on-chip may quickly subsume the physical space required for the placement of those components.
Many processors are now available in which a processor has the ability for its system clock to be stopped so that special on-chip test circuitry may be activated. Under the control of a test clock, the test circuitry reads and writes scan latches and registers throughout the chip. As one example, one of these registers may be internal to an instruction execution unit in the processor. The data is scanned out so that an examination may be made of the contents of the internal register at the time that the processor clock was stopped. A different value may then be written into the register and the processor clock restarted. In this manner, a development engineer may test and debug the hardware design of the processor circuitry.
There is often a need to set mode registers or especially to check status registers while the chip is functionally running without stopping system clocks and performing test clock operations. Additionally, for some designs, stopping system clocks causes the chip to be non-restartable without a full power-on-reset of the system because stopping system clocks may perturb the synchronization of the chips in the system.
In other known designs, many of the configurable mode bits must be brought out as pins on the chip module and configured on the system planar. As computer chips become more complex, there is an increasing number of mode bits requiring too many pins. Often, the pins are hardwired on the system planar and not usually software configurable. An alternate solution to mode pins is to use configuration registers on the chip, but similarly, as the chips become more complex, this large number of configuration wires cannot be feasible sourced by a single on-chip unit but instead needs to be distributed throughout the system.
Therefore, it would be advantageous to have an improved communication system and protocol for dedicated configuration and test circuitry that minimizes the amount of dedicated circuitry and wire congestion.
A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that connects a plurality of satellites in a daisy-chain fashion to a central source. Each on-chip satellite is associated with a unique identifier. In response to a determination that the transaction is accepted by the satellite, which is determined by the address in the address packet positively comparing to a unique identifier for the satellite, the address packet is modified to provide a positive acknowledgment of a receipt of the address packet back to the central source of the transaction. The address packet is modified by clearing the stop bit of the address packet, i.e. gating off or negating the stop bit. Alternatively, the address packet is otherwise modified to indicate the acceptance of the packet. The source of the address packet will identify that the operation was successful by detecting that the stop bit is cleared from the framed address packet, thereby receiving the positive acknowledgment indication, thus indicating that a successful transaction occurred.